1. Field of the Invention
The present invention relates to an output buffer circuit particularly, but not exclusively, for a semiconductor integrated circuit device (LSI).
2. Description of the Related Art
FIG. 10 is a circuit diagram showing a construction of a conventional output buffer circuit. This output buffer circuit has been widely used in complementary metal oxide semiconductors (will as called as "CMOSs" hereinafter) using P-channel type metal oxide semiconductor field effect transistors (will be called as "P-channel type MOS field effect transistors" hereinafter) and N-channel type metal oxide semiconductor field effect transistors (will be called as "N-channel type MOS field effect transistors" hereinafter).
In FIG. 10, an output buffer circuit 10 includes first and second CMOS inverters I1 and I2. First CMOS inverter I1 includes a P-channel type MOS field effect transistor P1 and an N-channel type MOS field effect transistor N1. Second CMOS inverter I2 includes a P-channel type MOS field effect transistor P2 and an N-channel type MOS field effect transistor N2.
Transistor P1 is connected between a power supply terminal Vcc for receiving a positive power supply potential (e.g., +5 V) and an output node O1. Transistor N1 is connected between a ground terminal Gnd for receiving a grand potential (0 V) and an output node O1. Gates of transistors P1 and N1 are connected to an input terminal IN. Transistor P2 is connected between power supply terminal Vcc and an output terminal OUT. Transistor N2 is connected between ground terminal Gnd and output terminal OUT. Gates of transistors P2 and N2 are connected to output node O1.
Substrates (sources) of transistors P1 and P2 are connected to power supply terminal Vcc. Substrates (sources) of transistors N1 and N2 are connected to grand terminal Gnd.
Input terminal IN is connected to an internal circuit 2. Internal circuit 2 and an output buffer circuit 10 is formed on a semiconductor chip CH. Output terminal OUT is wire-bonded to an external lead (external output terminal) OL of a package PAC. External lead OL is connected to an external element 3 of other LSI.
"Li" indicates an inductance, which is parasitically accompanied to an aluminium wire and a package internal interconnection line. "CL" indicates an external load capacity existing between external lead OL and external element 3, and includes an input capacity of external element 3, an interconnection line capacity and a package capacity of package PAC.
An operation of output buffer circuit in FIG. 10 will be described below with reference to an operation waveform diagram of FIG. 11.
When an input signal of "H" (e.g., +5 V) is applied to input terminal IN, transistor P1 is cut off, and transistor N1 is turned on. Thereby, output node 01 is short-circuited to grand terminal Gnd through transistor N1, and an output signal of output node 01 becomes "L" (ground potential). Thus, transistor P2 is turned on, and transistor N1 is cut off. Thereby, an output signal of output terminal OUT becomes "H" (+5 V).
Conversely, when input signal of "L" (e.g., 0 V) is applied to input terminal IN, transistor P1 is turned on, and transistor N1 is cut off. Thereby, output node 01 is short-circuited to power supply terminal Vcc through transistor P1, and output signal of output node 01 becomes "H" (+5 V). Thus, transistor P2 is cut off, and transistor N2 is turned on. Thereby, the output signal of output terminal OUT becomes "L".
In this manner, the input signal applied to input terminal IN is delayed for a delay time of output buffer circuit 10, as shown in FIG. 11, and the output signal of the same polarity as the input signal is obtained at output terminal OUT.
In FIG. 11, an abscissa represents a time, and an ordinate represents a voltage. "IN" represents a waveform of the input signal at input terminal IN, and "OUT" represents a waveform of the output signal at output terminal OUT.
Propagation delay times of first and second CMOS inverters I1 and I2 in the conventional output buffer circuit described above are determined by charging/discharging times of a load capacitance (output capacitance), which is primarily formed of a stray capacitance of the circuit, an input capacitance of a gate at a subsequent stage and others. The charging/discharging times are proportional to a product of a value of output capacitance CL and a value of ON-resistance of transistor P2 or N2.
Therefore, assuming that output capacitance CL has a constant value, the delay time of the second CMOS inverter I2 is determined by the ON-resistance of transistor P2 or N2.
In the output buffer circuit for driving a large current, it is necessary to design transistor P2 or N2 to have a small ON-resistance. This reduces the charging or discharging time of output capacitance CL of the output buffer circuit, i.e., a rising or falling time of the output voltage, resulting in rapid rising or falling of the output voltage waveform.
In addition to output capacitance CL, inductance L1 is added to output terminal OUT. Further, undershoot is caused in the output waveform during the falling operation, and overshoot is caused in the output waveform during the rising operation, because an impedance of output buffer circuit 10 is not matched with an impedance of the external circuit. Particularly, since an interface at a TTL level has a logical threshold of about 1.6 V which is close to the ground potential, wrong operation of external equipments may be caused due to the undershoot.
Owing to the recent development of the fine working technology, the semiconductor devices have been highly integrated, and operation speeds of gates in the integrated circuits have increased, whereby the responsibility of the output buffer circuits has also increased. This increases the significance of the above problem.